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73S8023C Smart Card Interface
Simplifying System IntegrationTM
DATA SHEET
April 2009
DESCRIPTION
The Teridian 73S8023C is a low-power, high efficiency, single smart card interface IC suitable for 3V and 5V cards. It provides full electrical compliance with ISO7816-3 and EMV 4.0 (EMV2000) specifications. Hardware support for any type of synchronous cards (memory cards) is provided. Interfacing with the system controller is done through the control bus; composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. Data exchange with the card is managed from the system controller using the I/O line (and eventually the auxiliary I/O lines). A chip select input allows multiple 73S8023C ICs to share the same control bus. When chip select is set low, the host microcontroller inputs are latched and outputs are taken to a high impedance state. The card clock signal can be generated by an on-chip oscillator using an external crystal or by connecting an external clock signal. The 73S8023C device incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The 73S8023C requires only a single 2.7 V to 3.6 V power supply, and features a high-efficiency embedded DC-DC converter. This architecture, plus a Power Down digital input that allow placing the IC in a very low-power mode making the 73S8023C particularly suitable for low-power applications (cell-phones, PDAs, payphones, hand-held POS terminals...).
FEATURES
* Card Interface: Complies with ISO-7816-3, EMV 4.0 A DC-DC Converter provides 3V / 5V to the card from an external power supply input High-efficiency converter: > 80% @ V DD =3.3 V, V CC =5 V and I CC = 65 mA Up to 100 mA supplied to the card ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation Protection includes 2 voltage supervisors which detect voltage drops on card V CC and on V DD power supply The V DD voltage supervisor threshold value can be externally adjusted True over-current detection (150 mA max.) 2 card detection inputs, 1 for either possible switch configuration Full support of synchronous cards System Controller Interface: 3 Digital inputs control the card activation / deactivation, card reset and card voltage 3 Digital inputs control the card clock (division rate and card clock source selection) 1 Digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults 1 Power down digital input (places the 73S8023C in a very low-power mode (card deactivated) 1 Chip select digital input for parallel operation of several 73S8023C ICs. 1 External clock input (STROBE), used for synchronous operation 1 Digital output clock, buffered version of signal on XTALIN Crystal oscillator or host clock (XTALIN), up to 27 MHz Power Supply: V DD 2.7 V to 3.6 V 6 kV ESD Protection on the card interface
*
ADVANTAGES
* * * Supports both synchronous and asynchronous smart cards Replacement for TDA8002, with up to 600 mW in power savings (@ EMV ICCmax condition) ! The inductor-based DC-DC converter provides higher current and efficiency Ideal for battery-powered applications Suitable for high current cards and SAMs: (100 mA max) Single 2.7 V to 3.6 V power supply allows removal of 5 V from the system Power down mode: 2 A typical Package: Small Format (5x5mm) 32-QFN
* *
APPLICATIONS
* * * * Point of Sales and Transaction Terminals Payphones Set-Top-Boxes, DVD / HDD Recorders Payment card interfaces in portable devices (PDAs, mobile phones...)
* *
Rev. 1.5
(c) 2009 Teridian Semiconductor Corporation
1
73S8023C Data Sheet FUNCTIONAL DIAGRAM
VDD 20 4 NC 21 GND VDDF_ADJ 17 LIN 6 2 VDD 3 6
DS_8023C_019
VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE
ICC FAULT VDD FAULT VCC FAULT
1 GND
5 PWRDN
DC-DC CONVERTER
12 GND 15 VCC
CS CMDVCC RSTIN
8 18 19 31
R-C OSC. DIGITAL CIRCUITRY & FAULT LOGIC
Int_Clk
ICC RESET BUFFER
14 RST
5V/3V 22 OFF 29 CLKDIV1 30 CLKDIV2 23 XTALIN 24 XTALOUT 32 CLKOUT
ICC CLOCK BUFFER
13 CLK 25 STROBE
ISO-7816-3 SEQUENCER XTAL OSC CLOCK GENERATION OVER TEMP
TEMP FAULT
16 CLKSEL 7 PRES 6 PRES
9 26 IOUC 27 AUX1UC 28 AUX2UC I/O
ICC I/O BUFFERS
11 AUX1 10 AUX2
Figure 1: 73S8023C Block Diagram
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73S8023C Data Sheet
Table of Contents
1 Pin Description .................................................................................................................................... 5 1.1 Card Interface ............................................................................................................................... 5 1.2 Miscellaneous Inputs and Outputs................................................................................................ 5 1.3 Power Supply and Ground............................................................................................................ 5 1.4 Microcontroller Interface ............................................................................................................... 6 System Controller Interface ............................................................................................................... 7 Oscillator.............................................................................................................................................. 8 DC-DC Converter - Card Power Supply .......................................................................................... 8 Voltage Supervision ........................................................................................................................... 9 Power Down....................................................................................................................................... 10 Over-Temperature Monitor............................................................................................................... 10 Activation and Deactivation ............................................................................................................. 11 8.1 Activation Sequence (Synchronous Mode) ................................................................................ 11 8.2 Deactivation Sequence (Synchronous Mode) ............................................................................ 11 8.3 Activation Sequence (Asynchronous Mode) ............................................................................... 12 8.4 Deactivation Sequence (Asynchronous Mode) .......................................................................... 14 OFF and Fault Detection .................................................................................................................. 14 I/O Circuitry and Timing ................................................................................................................... 15 Typical Application Schematic ........................................................................................................ 17 Electrical Specification..................................................................................................................... 18 12.1 Absolute Maximum Ratings ........................................................................................................ 18 12.2 Recommended Operating Conditions......................................................................................... 18 12.3 Package Thermal Parameters .................................................................................................... 18 12.4 Card Interface Characteristics .................................................................................................... 19 12.5 Digital Signals ............................................................................................................................. 22 12.6 DC Characteristics ...................................................................................................................... 23 12.7 Voltage / Temperature Fault Detection Circuits.......................................................................... 23 Mechanical Drawing (32-QFN) ......................................................................................................... 24 Package Pin Designation (32-QFN) ................................................................................................. 25 Ordering Information ........................................................................................................................ 26 Related Documentation .................................................................................................................... 26 Contact Information .......................................................................................................................... 26
2 3 4 5 6 7 8
9 10 11 12
13 14 15 16 17
Revision History ........................................................................................................................................ 27
Rev. 1.5
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73S8023C Data Sheet
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Figures
Figure 1: 73S8023C Block Diagram ............................................................................................................. 2 Figure 2: Power Down Mode Operation: CS = high.................................................................................... 10 Figure 3: Activation Sequence - Synchronous Mode ................................................................................. 11 Figure 4: Synchronous Deactivation Operation - CKSEL = High............................................................... 12 Figure 5: Asynchronous Activation Sequence - RSTIN Low When CMDVCC Goes Low ......................... 13 Figure 6: Asynchronous Activation Sequence - Timing Diagram #2 ......................................................... 13 Figure 7: Asynchronous Deactivation Sequence ........................................................................................ 14 Figure 8: Timing Diagram - Management of the Interrupt Line OFF .......................................................... 15 Figure 9: I/O and I/OUC State Diagram ...................................................................................................... 16 Figure 10: I/O - I/OUC Delays Timing Diagram.......................................................................................... 16 Figure 11: 73S8023C - Typical Application Schematic .............................................................................. 17 Figure 12: DC - DC Converter efficiency (V CC = 5 V) ................................................................................ 20 Figure 13: DC - DC Converter Efficiency (V CC = 3 V) ................................................................................ 20 Figure 14: 32-QFN Mechanical Drawing..................................................................................................... 24 Figure 15: 32-QFN 73S8023C Pin Out ....................................................................................................... 25
Table
Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 8
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73S8023C Data Sheet
1 Pin Description
1.1
I/O AUX1 AUX2 RST CLK PRES PRES VCC GND
Card Interface
Pin 9 11 10 14 13 7 6 15 12 Description Card I/O: Data signal to/from card. Includes a pull-up resistor to V CC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V CC. Card reset: Provides reset (RST) signal to card. Card clock: Provides clock (CLK) signal to card. The rate of this clock is determined by crystal oscillator frequency and CLKDIV selections. Card Presence switch: Active high indicates card is present. Includes a pull-down current source. Card Presence switch: Active low indicates card is present. Includes a pull-up current source. Card power supply: Logically controlled by sequencer, output of DC-DC converter. Requires an external filter capacitor to the card GND. Card ground.
Name
1.2
Miscellaneous Inputs and Outputs
Pin 23 24 17 4 Description Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. V DD fault threshold adjustment input: this pin can be used to adjust V DDF value (that controls deactivation of the card). Must be left open if unused. Non-connected pin. Must be left open.
Name XTALIN XTALOUT VDDF_ADJ NC
1.3
Power Supply and Ground
Pin 3, 20 1 21 2 Description System controller interface supply voltage: Supply voltage for internal power supply and DC-DC converter power supply source. DC-DC converter ground. Digital ground. External inductor. Connect external inductor from pin 2 to V DD . Keep the inductor close to pin 2.
Name VDD GND GND LIN
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73S8023C Data Sheet
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1.4
Microcontroller Interface
Pin 18 Description Command V CC (negative assertion): Logic low on this pin causes the DC-DC converter to ramp the V CC supply to the card and initiates a card activation sequence. 5 volt / 3 volt card selection: Logic one selects 5 volts for V CC and card interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or V DD . However, it includes a high impedance pull-up resistor to default this pin high (selection of 5V card) when unconnected Power Down control input: Active High. When Power Down (PD) mode is activated, all internal analog functions are disabled to place the 73S8023C in its lowest power consumption mode. The PD mode is allowed only out of a card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to ground when power down function is not used. Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card clock. These pins include pull-down resistors. CLKDIV1 0 0 1 1 CLKDIV2 0 1 1 0 Clock Rate XTALIN/8 XTALIN/4 XTALIN/2 XTALIN
Name CMDVCC
5V/#V
31
PWRDN
5
CLKDIV1 CLKDIV2
29 30
OFF
22
Interrupt signal to the processor: Active Low. Multi-function indicating fault conditions and card presence. Open drain output configuration; it includes an internal 20 k pull-up to V DD. Reset Input: This signal controls the RST signal to the card. System controller data I/O to/from the card. Includes internal pull-up resistor to V DD. System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to V DD. System controller auxiliary data I/O to/from the card. Includes internal pull-up resistor to V DD. When CS = 1, the control and signal pins are configured normally. When CS is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2, CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high impedance pull-up mode and won't pass data to or from the smart card. OFF output is tri-stated. Selects CLK and RST operational mode. When CLKSEL is low (default), the circuit is configured for asynchronous card operation and the sequencer manages the control of CLK and RST. When CLKSEL is high, the signal CLK is a buffered copy of STROBE and the signal RST is directly controlled by RSTIN. When CLKSEL = 1, the signal CLK is controlled directly by STROBE. CLKOUT is the buffered version of the signal on pin XTALIN.
RSTIN I/OUC AUX1UC AUX2UC CS
19 26 27 28 8
CLKSEL
16
STROBE CLKOUT
25 32
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73S8023C Data Sheet
2 System Controller Interface
* The CS (chip select) input allows multiple devices to operate in parallel. When CS is high, the system interface signals operate as described. When CS is taken low, the system interface signals are latched internally. The pins I/OUC, AUX1UC, and AUX2UC are weakly pulled up and the OFF signal is put into a high impedance state. The CLKSEL signal selects between synchronous and asynchronous operation. When CLKSEL is low, asynchronous operation is selected. When CLKSEL is high, synchronous operation is selected. Digital inputs allow direct control of the card interface from the host as follows: Pin CMDVCC: When set low, starts an activation sequence if a card is present. Pin 5V/#V: Defines the card voltage. The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to the host: Pin RSTIN: controls the card RST signal. When enabled by the sequencer, RST is equal to RSTIN for both synchronous and asynchronous modes. Pin I/OUC: data transfer to card I/O contact. Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/Os which are connected to the C4 and C8 card connector contacts). Two digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card clock frequency from the input clock frequency (crystal or external clock). The division rate is defined as follows: CLKDIV2 0 0 1 1 CLKDIV1 0 1 0 1 CLK
* *
*
*
XTAL
XTAL 1/4 XTAL 1/2 XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN. When other division rates are used, the 73S8023C circuitry guarantees a duty-cycle in the range 45% to 55%, conforming to ISO-7816-3 and EMV 4.1 specifications. * Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card removedl during a card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence. Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8023C in its Power Down state. This pin can only be activated outside of a card session. The CLKOUT signal is a buffered output of the signal applied to the XTALIN pin whether it is an external clock source or it is configured as a crystal oscillator. CLKOUT can be used when using multiple 73S8023C devices to share a single clock signal. The STROBE input directly drives the smart card CLK signal when operating in synchronous mode. STROBE is ignored in asynchronous mode.
* *
*
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73S8023C Data Sheet
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3 Oscillator
The 73S8023C device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. Signal CLKOUT is the buffered version of the signal on XTALIN.
4 DC-DC Converter - Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either 3 V or 5 V card voltage from the power supply applied on the V DD pin. The digital ISO-7816-3 sequencer controls the converter. Card voltage selection is carried out by the digital input 5V/#V. The circuit is an inductive step-up converter/regulator. The external components required are 2 filter capacitors on the power-supply input V DD (next to the LIN pin, 100 nF + 10 F), an inductor, and an output filter capacitor on the card power supply V CC . The circuit performs regulation by activating the step-up operation when V CC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the input supply V DD is less than the set point for V CC . When V DD is greater than the set point for V CC (V DD = 3.6 V, V CC =3 V) the circuit operates as a linear regulator. Depending on the inductor values, the voltage converter can provide current on V CC as high as 100 mA. The circuit provides over-current protection and limits I CC to 150 mA. When an over-current condition is sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host controller a fault on the interrupt output OFF. Choice of the inductor The nominal inductor value is 10 H, rated for 400 mA. The inductor is connected between LIN (pin 2) and the V DD supply voltage. The inductor value can be optimized to meet a particular configuration (I CC_MAX ). The inductor should be located on the PCB as close as possible to the LIN pin of the IC. Choice of the V CC capacitor Depending on the applications, the requirements in terms of both the V CC minimum voltage and the transient currents that the interface must provide to the card are different. Table 1 shows the recommended capacitors for each V CC power supply configuration and applicable specification. Table 1: Choice of VCC Pin Capacitor Specification Requirement Specification EMV 4.1 ISO-7816-3 NDS Min V CC Voltage Allowed During Transient Current 4.6 V 4.5 V 4.65 V Max Transient Current Charge 30 nAs 20 nAs 40 nAs Application Capacitor Type X5R/X7R w/ ESR < 100 m Capacitor Value 3.3 F 1 F 3.3 F
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73S8023C Data Sheet
5 Voltage Supervision
Two voltage supervisors constantly check the presence of the voltages V DD and V CC . A card deactivation sequence is triggered upon a fault detected by these voltage supervisors. The digital circuitry is powered by the power supply applied on the VDD pin. V DD also defines the voltage range for the interface with the system controller. The V DD Voltage supervisor is also used to initialize the ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The voltage threshold of the V DD voltage supervisor is internally set by default to 2.3 V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 17) is used to connect an external resistor R EXT to ground to raise the V DD fault voltage to another value, V DDF . The resistor value is defined as follows: R EXT = 180 k /(V DDF - 2.33) An alternative (more accurate) method of adjusting the V DD fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see Figure 11: 73S8023C - Typical Application Schematic). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.649 / V TH ) - 0.6042 where V TH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas: R3 = 72000 / Kx R1 = R3*(Kx / (1 - Kx))
Taking the example above, where a V DD fault threshold voltage of 2.7 V is desired, solving for Kx gives: Kx = (2.649 / 2.7) - 0.6042 = 0.377 Solving for R3 gives: Solving for R1 gives: R3 = 72000 / 0.377 = 191 k. R1 = 191000 *(0.377 / (1 - 0.377)) = 115.6 k.
Using standard 1 % resistor values gives R3 = 191 k and R1 = 115 k. These values give an equivalent resistance of Kx = 0.376, a 0.3% error. Using 1% external resistors and a parallel resistance of 72 k ohms will result in a +/- 6% tolerance in the value of VDD Fault. The sources of variation due to integrated circuit process variations and mismatches include the internal reference voltage (less than +/- 1%), the internal comparator hysteresis and offset (less than +/- 1.7% for part-to-part, processing and environment), the internal resistor value mismatch and value variations (less than 1.8%), and the external resistor values (1%). If the 2.3 V default threshold is acceptable, this pin must be left unconnected.
Rev. 1.5
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73S8023C Data Sheet
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6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down (PD) mode disables all the internal analog functions, including the card analog interface, the oscillators and the DC-DC converter, to put the 73S8023C in its lowest power consumption mode. PD mode is only allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from the host controller). The host controller invokes the power down state when it is desirable to save power. The signals PRES and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller must then set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to turning CMDVCC low). Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators and reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms time period. If a card is present, OFF can be used as an indication that the circuit has completed its recovery from power-down state. OFF will go high at the end of the stabilization period. Should CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on its edges, it should be toggled high and low again after the 10 ms to activate a card. Figure 2 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if the power down function is not used.
PRES OFF PWRDN Internal RC OSC
~10ms
OFF follows PRES regardless of PWRDN
PWRDN during a card session has no effect
PWRDN has effect when the cardi s deactivated
CMDVCC
After setting PWRDN = 0, the controller must wait at least 10ms before setting CMDVCC=0
EMV / ISO deactivation time ~= 100 uS
Figure 2: Power Down Mode Operation: CS = high
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
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73S8023C Data Sheet
8 Activation and Deactivation
8.1 Activation Sequence (Synchronous Mode)
The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application of V DD > V DDF . No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to activate the card. The following steps list the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low: 1. CMDVCC is set low. 2. Turn on V CC and I/O (AUX1, AUX2) to reception mode at the end of (t ACT ). 3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t 1 ).
CMDVCC VCC IO RSTIN RST
STROBE CLK
tACT
t1
tACT ~= 500s t1 > 0.5s after tACT, RST = RSTIN, CLK = STROBE Figure 3: Activation Sequence - Synchronous Mode
8.2
Deactivation Sequence (Synchronous Mode)
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, V DD fault and card extraction during the session and are indicated to the system controller by the fall of OFF. The following steps list the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or a fault condition sets OFF low: 1. 2. 3. 4. RST goes low at time t 1 . CLK stops low at time t 2 . I/O goes low at time t 3 . Out of reception mode. V CC is shut down at time t 4 . After a delay t 5 (discharge of the V CC capacitor), V CC is low.
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73S8023C Data Sheet
CMDVCC OFF -- OR --
DS_8023C_019
VCC IO RSTIN RST STROBE CLK
t0 t1 t2 t3
t4
t5
t0 - Deactivation starts after CMDVCC is set high or OFF falls due to card removal or fault t1 - RST falls approx. 0.5us after deactivation begins t2 - CLK falls approx. 7.5us after RST falls t3 - IO falls approx 2us after CLK falls t4 - VCC is shut down t5 - VCC goes to 0 after discharge of VCC capacitor, approx 100us after deactivation begins (Note: Host should set STROBE low when CMDVCC is set high, otherwise CLK may be truncated. CLK truncation may occur if an OFF event is triggered)
Figure 4: Synchronous Deactivation Operation - CKSEL = High
8.3
Activation Sequence (Asynchronous Mode)
The 73S8023C smart card interface IC has an internal 10 ms delay at power-on reset or upon application of V DD > V DDF or upon exit of Power Down mode. The card interface may only be activated when OFF is high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to activate the card. The following steps list the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: 1. CMDVCC is set low. 2. Next, the internal V CC control circuit checks the presence of V CC at the end of t 1 . In normal operation, the voltage V CC to the card becomes valid during t 1 . If V CC does not become valid, then OFF goes low to report a fault to the system controller, and the power V CC to the card is turned off. 3. Turn I/O (AUX1, AUX2) to reception mode at the end of t 2 . 4. CLK is applied to the card at the end of t 3 . 5. RST is a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer won't set RST high until 42000 clock cycles after the start of CLK.
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73S8023C Data Sheet
CMDVCC VCC IO CLK RSTIN RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator) t2 = 1.5 s, I/O goes to reception state t3 0.5 s, CLK starts t4 42000 card clock cycles. Time for RST to become the copy of RSTIN Figure 5: Asynchronous Activation Sequence - RSTIN Low When CMDVCC Goes Low The following steps list the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: 1. CMDVCC is set low. 2. Next, the internal V CC control circuit checks the presence of V CC at t 1 . In normal operation, the voltage V CC to the card becomes valid during this time. If not, OFF goes low to report a fault to the system controller, and the power V CC to the card is turned off. 3. Due to the fall of RSTIN at t 2 , turn I/O (AUX1, AUX2) to reception mode. 4. CLK is applied to the card at the end of t 3 after I/O is in reception mode. 5. RST is to be a copy of RSTIN after t 4 . RSTIN may be set high before t 4 , however the sequencer won't set RST high until 42000 clock cycles after the start of CLK.
CMDVCC VCC IO CLK RSTIN RST
t1
t2
t3
t4
t1 t2 t3 t4
= 0.510 ms (timing by 1.5MHz internal Oscillator) = 1.5s, I/O goes to reception state = > 0.5s, CLK active 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 6: Asynchronous Activation Sequence - Timing Diagram #2
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73S8023C Data Sheet
DS_8023C_019
8.4
Deactivation Sequence (Asynchronous Mode)
Deactivation is initiated either by the system controller by setting CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, V DD fault, V CC fault, and card extraction during the session. The following steps list the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: 1. 2. 3. 4. RST goes low at the end of time t 1 . CLK stops low at the end of time t 2 . I/O goes low at the end of time t 3 . Out of reception mode. V CC is shut down at the end of time t 4 . After a delay t 5 (discharge of the V CC capacitor), V CC is low.
CMDVCC -- OR -OFF
RST CLK I/O VCC
t1
t2
t3
t4
t5
t1 0.5 s, timing by 1.5 MHz internal Oscillator t3 0.5 s t4 0.5 s t2 7.5 s t5 = depends on VCC filter capacitor. t1 + t2 + t3 + t4 + t5 ~= 100 s Figure 7: Asynchronous Deactivation Sequence
9 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Monitoring Outside a Card Session In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. Monitoring During a Card Session CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same time that OFF is set low, the sequencer starts the deactivation process. Figure 8 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside the card session:
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73S8023C Data Sheet
OFF is low by card extracted
PRES OFF CMDVCC VCC
OFF is low by any fault
outside card session
within card session
within card session
Figure 8: Timing Diagram - Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The I/O, AUX1, and AUX2 pins are in the low state after power-on reset and they are in the high state when the activation sequencer turns on the I/O reception state. See Section 8 Activation and Deactivation for more details on when the I/O reception is on. The state of the I/OUC, AUX1UC, and AUX2UC pins is high after power-on reset. Within a card session and when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both I/O lines return to their neutral state. Figure 9 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 10. In order to be compliant to the NDS specifications, a 27 pF capacitor must be added between pins I/O (C7) and GND (C5) at the smart card connector.
Rev. 1.5
15
73S8023C Data Sheet
DS_8023C_019
Neutral State
No
I/O reception
Yes
I/O & not I/OUC
No Yes No I/OUC & not I/O Yes I/OUC in No I/OICC in No
I/OUC
I/O
yes
yes
Figure 9: I/O and I/OUC State Diagram
IO
IOUC
tIO_HL
Delay from I/O to I/OUC: Delay from I/OUC to I/O:
tIO_LH
tIOUC_HL
tIOUC_LH
t IO_HL = 100ns t IO_LH = 25ns t I/OUC_HL = 100ns t I/OUC_LH = 25ns
Figure 10: I/O - I/OUC Delays Timing Diagram
16
Rev. 1.5
73S8023C Data Sheet
DS_8023C_019
11 Typical Application Schematic
AUX2UC_to/from_uC AUX1UC_to.from_uC I/OUC_to/from_uC STROBE_from_uC CLKDIV1_from_uC CLKDIV2_from_uC 5V/3V_select_from_uC CLKOUT_to_uC
CLKOUT 32 5V/3V 31 CLKDIV2 30 CLKDIV1 29 AUX2UC 28 AUX1UC 27 I/OUC 26 STROBE 25
See NOTE 6
See NOTE 3 See note 7 VDD VDD C4 C5 100nF See note 2 - OR R3 Rext2 24 23 22 21 20 19 18 17 R1 Rext1 32QFN External_clock_from uC
VDD See NOTE 1 10uF
L1
10uH
C2 22pF VDD See NOTE 1 C9 100nF Y1 CRYSTAL See NOTE 4 C3 22pF
PWRDN_from_uC See NOTE 5
1 2 3 4 5 6 7 8
GND LIN VDD NC PWRDN PRES PRES CS
XTALOUT XTALIN OFF GND 73S8023C VDD RSTIN CMDVCC VDDF_ADJ
CLKSEL_from_uC OFF_interrupt_to_uC
NOTES: 1) VDD supply must be = 2.7V to 3.6V DC). VDD 2) Keep L1 close to pin 2. 3) Required if external clock from uP is used. R2 4) Required if crystal is used. 20K Y1, C2 and C3 must be removed if external clock is used. 5) Pin can not float. Must be driven or connected to GND if power down function is not used. 6) Internal pull-up allows it to be left open if unused. 7) Rext1 and Rext2 are external resistors to ground and VDD to modify the VDD fault voltage. Can be left open. 8) Capacitors C7 and C8 are optional. C6 is mandatory for NDS.
27pF 27pF C6 C7 C8 27pF SO7816=1uF, NDS/EMV=3.3uF C1 Low ESR (<100mohms) C1 should be placed near the SC connecter contact
9 10 11 12 13 14 15 16
CS_from_uC
I/O AUX2 AUX1 GND CLK RST VCC CLKSEL
RSTIN_from_uC CMDVCC_from_uC
10 9
Card detection switch is normally closed.
SW-2 SW-1
C8 I/O VPP GND C4 CLK RST VCC
8 7 6 5 4 3 2 1
CLK track should be routed far from RST, I/O, C4 and C8.
Smart Card Connector
Figure 11: 73S8023C - Typical Application Schematic
Rev. 1.5
17
73S8023C Data Sheet
DS_8023C_019
12 Electrical Specification
12.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device. Parameter Supply Voltage V DD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except LIN and card interface) Pin Voltage (LIN) Pin Voltage (card interface) ESD Tolerance - Card interface pins ESD Tolerance - Other pins Rating -0.5 to 4.0 VDC -0.3 to (V DD +0.5) VDC -60 C to 150 C -0.3 to (V DD +0.5) VDC -0.3 to 6.0 VDC -0.3 to (V CC + 0.5) VDC +/- 6 kV +/- 2 kV
ESD testing on Card pins uses the HBM condition, 3 pulses, each polarity referenced to ground. The smart card pins are protected against shorting between any combination of smart card pins.
12.2 Recommended Operating Conditions
Parameter Supply Voltage V DD Ambient Operating Temperature Input Voltage for Digital Inputs Rating 2.7 to 3.6 VDC -40 C to +85 C 0 V to V DD + 0.3 V
12.3 Package Thermal Parameters
Package 32QFN 32QFN Rating 47 C / W (with bottom pad soldered) 78 C / W (without bottom pad soldered)
18
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
12.4 Card Interface Characteristics
Symbol Parameter Condition Min Typ Max Unit
Card Power Supply (V CC ) DC-DC Converter General conditions, -40 C < T < 85 C, 2.7 V < V DD < 3.6 V Inactive mode Inactive mode I CC =1 mA Active mode I CC < 65 mA; 5 V Active mode I CC < 65 mA; 3 V Active mode single pulse of 100 mA for 2 s; 5 V, fixed load = 25 mA Active mode single pulse of 100 mA for 2 s; 3 V, fixed load = 25 mA Active mode current pulses of 40 nAs with peak |I CC | < 200 mA, t < 400 ns; 5 V Active mode current pulses of 40 nAs with peak |I CC | < 200 mA, t < 400 ns; 3 V V CCR I CCmax I CCF V SR V SF CF L Limax VCC Ripple Maximum supply current to the card I CC fault current V CC slew rate - Rise rate on activate V CC slew rate - Fall rate on deactivate External filter capacitor (V CC to GND) Inductor (LIN to V DD ) Imax in inductor Efficiency V CC = 5 V, I CC = 65 mA, V DD = 2.7 V V CC = 5 V, I CC = 65 mA, V DD = 3.3 V 87 C F on V CC = 1 uF C F on V CC = 1 uF Static load current V CC > 4.6 or 2.7 V as selected, L=10 H 100 100 0.05 0.1 0.47 125 0.15 0.3 3.3 10 400 180 0.25 0.5 4.7 -0.1 -0.1 4.75 2.8 0.1 0.4 5.25 3.2 V V V V
4.65
5.25
V
V CC
Card supply voltage including ripple and noise
2.76
3.2
V
4.65
5.25
V
2.76
3.2 350
V mV mA mA V/s V/s F H mA %
Rev. 1.5
19
73S8023C Data Sheet
DS_8023C_019
1011B01 Converter efficiency (VCC 5V)
Converter Efficiency (VCC 5 V)
100 95 90 85
Efficiency [%]
80 75 70 65 60 55 50 0 20 40 Icc [mA] 60 80 100 2.7V 3.0V 3.3V 3.6V
Figure 12: DC - DC Converter efficiency (V CC = 5 V) Output current on Vcc at 5 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts.
1011B01 Converter efficiencyCC 3 V) Converter Efficiency (V (VCC 3V) 100 95 90 85
Efficiency [%]
80 75 70 65 60 55 50 0 20 40 Icc [mA] 60 80 100 2.7V 3.0V 3.3V (Linear) 3.6V (Linear)
Figure 13: DC - DC Converter Efficiency (V CC = 3 V) Output current on Vcc at 3 V. Input voltage on V DD at 2.7, 3.0, 3.3 and 3.6 volts. 20 Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. I SHORTL , I SHORTH , and V INACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC. V OH V OH V OL V IH V IH V IL V INACT I LEAK Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low Output voltage when outside of session Input leakage Input current, low (I/OUC, AUX1UC, AUX2UC) Input current, low (I/O, AUX1, AUX2) I SHORTL Short circuit output current I OL = 0 I OL = 1 mA V IH = V CC V IL = 0, CS = 1 V IL = 0, CS = 0 V IL = 0 For output low, shorted to V CC through 33 For output high, shorted to ground through 33 C L = 80 pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, C L = 50 pF Output stable for > 200 ns For pins IOUC, AUX1UC, AUX2UC when CS = 0 I OH = 0 1 I OH = -40 A I OH = 0 I OH = -40 A I OL =1 mA 1.8 1.8 -0.3 0.9 V CC 0.75 V CC 0.9 V DD 0.75 V DD V CC + 0.1 V CC + 0.1 V DD + 0.1 V DD + 0.1 0.3 V CC + 0.30 V DD + 0.30 0.8 0.1 0.3 10 0.65 5 2 15 V V V V V V V V V V A mA A mA mA
I IL
I SHORTH
Short circuit output current
15
mA
tR, tF t IR , t IF R PU Ipuhiz FD MAX
Output rise time, fall times Input rise, fall times Internal pull-up resistor Pull-up current, Hi-Z state Maximum data rate Delay, I/O to I/OUC, I/OUC to I/O (falling edge to falling edge) Delay, I/O to I/OUC, I/OUC to I/O (rising edge to rising edge) Input capacitance
100 1 8 11 14 5 1 100 Started
ns s k A
MHz
T FDIO
ns 10 10 pF
C IN
1
NDS applications require a 27 pF capacitor on I/O placed at the smart card connector. 21
Rev. 1.5
73S8023C Data Sheet Symbol V OH V OL V INACT I RST_LIM I CLK_LIM Parameter Output level, high Output level, low Output voltage when outside of a session Output current limit, RST Output current limit, CLK C L = 35 pF for CLK, 10% to 90% C L = 200 pF for RST, 10% to 90% CLKSEL = 1, Cap. load on CLK and RST is minimal, else rise, fall times are a factor C L = 35 pF, 48% < IN < 52% 45 Condition I OH = -200 A I OL = 200 A I OL = 0 I OL = 1 mA Min 0.9 V CC 0 Typ
DS_8023C_019 Max V CC 0.2 0.1 0.3 30 70 8 100 Unit V V V V mA mA ns ns
Reset and Clock for card interface, RST, CLK
tR, tF
Output rise time, fall time
Td
Delay time STROBE to CLK, RSTIN to RST
20
ns
Duty cycle for CLK
55
%
12.5 Digital Signals
Symbol V IL V IH V OL V OH R OUT t SL t DZ t IS t SI t ID t DI |I IL1 | Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-up resistor, OFF Time from CS going high to interface active Time from CS going low to interface inactive, Hi-Z Set-up time, control signals to CS rising edge Hold time, control signals from CS rising edge Set-up time, control signals to CS fall Hold time, control signals from CS fall Input Leakage Current GND < V IN < V DD -5 50 50 5 50 50 50 50 I OL = 2 mA I OH = -1 mA V DD - 0.45 20 Condition Min -0.3 1.8 Typ Max 0.8 V DD + 0.3 0.45 Unit V V V V k ns ns ns ns ns ns A
Digital I/O Except for OSC I/O
22
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
Symbol V ILXTAL V IHXTAL I ILXTAL f MAX in
Parameter Input Low Voltage - XTALIN Input High Voltage - XTALIN Input Current - XTALIN Max freq. Osc or external clock External input duty cycle limit
Condition
Min -0.3 0.7 V DD
Typ
Max 0.3 V DD V DD +0.3 30 27
Unit V V A MHz %
Oscillator (XTALIN) I/O Parameters
GND < V IN < V DD tR/F < 10% fIN, 45% < CLK < 55%
-30
48
52
12.6 DC Characteristics
Symbol Parameter Condition Linear mode, ICC = 0 I/O, AUX1, AUX2 = high Step up mode, ICC = 0 I/O, AUX1, AUX2 = high PWRDN = 1, Start/stop bit = 0 All digital inputs driven with a true logical 0 or 1 Min Typ 4.9 4.7 Max Unit mA mA
I DD
Supply Current on V DD
I DD_PD
Supply Current on V DD in Power Down mode
0.11
2.5
A
12.7 Voltage / Temperature Fault Detection Circuits
Symbol V DDF V CCF TF I CCF Parameter V DD fault - V DD Voltage supervisor threshold) V CC fault - V CC Voltage supervisor threshold Die over temperature fault Card over current fault Condition No external resistor on VDDF_ADJ V CC = 5 V V CC = 3 V Min 2.15 4.20 2.5 115 100 Typ Max 2.4 4.6 2.7 145 150 Unit V V V C mA
Rev. 1.5
23
73S8023C Data Sheet
DS_8023C_019
13 Mechanical Drawing (32-QFN)
5 2.5
0.85 NOM./ 0.9MAX. 0.00 / 0.005 0.20 REF.
1 2 3
2.5 5
SEATING PLANE
TOP VIEW
SIDE VIEW
0.35 / 0.45
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3
3.0 / 3.75
0.2 MIN. 0.35 / 0.45
Figure 14: 32-QFN Mechanical Drawing
0.25 1.5 / 1.875 0.5
0.5 0.25
BOTTOM VIEW
24
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
14 Package Pin Designation (32-QFN)
Use handling procedures necessary for a static sensitive component.
CLKDIV2
CLKDIV1
32
31
30
29
28
27
26
I/OUC
GND LIN VDD NC PRDWN PRES PRES CS
1 2 3 4 5 6 7 8
25
STROBE
CLKOUT
AUX2UC
AUX1UC
5V/3V
24 23 22
XTALOUT XTALIN OFF GND VDD RSTIN CMDVCC VDDF_ADJ
TERIDIAN 73S8023C
21 20 19 18 17
10
11
12
13
14
15 VCC
AUX1
(Top View) Figure 15: 32-QFN 73S8023C Pin Out
Rev. 1.5
CLKSEL
I/O
AUX2
CLK
GND
RST
16
9
25
73S8023C Data Sheet
DS_8023C_019
15 Ordering Information
Part Description 73S8023C-QFN 32-pin Lead-Free QFN 73S8023C-QFN 32-pin Lead-Free QFN Tape / Reel Order Number 73S8023C-IM/F 73S8023C-IMR/F Packaging Mark 73S8023C 73S8023C
16 Related Documentation
The following 73S8023C documents are available from Teridian Semiconductor Corporation: 73S8023C Data Sheet (this document) 73S8023C QFN Demo Board User's Guide
17 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8023C, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
26
Rev. 1.5
DS_8023C_019
73S8023C Data Sheet
Revision History
Revision 1.0 1.1 1.2 1.3 1.4 1.5 Date 6/13/2005 7/15/2005 12/5/2007 1/17/2008 1/8/2009 4/3/2009 Description First publication. Converted to Teridian format. Add EMV and ISO logo, remove leaded package option, change 32QFN punched to SAWN package. Changed dimension of bottom exposed pad on 32QFN mechanical package figure. Added NDS logo to page 1 and assigned document number. Removed all references to VPC as VPC must be tied to VDD.
(c) 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com Rev. 1.5 27

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